1. Field of the Invention
The present invention relates to a decoder circuit in an LCD drive apparatus.
2. Description of the Related Art
In a drive apparatus for driving a display apparatus such as a TFT (Thin Film Transistor) type LCD (Liquid Crystal Display) panel, there is a decoder circuit having a configuration called a tournament system (e.g., refer to Japanese Patent Application Laid-Open (JP-A) No. 2007-232977). The decoder circuit outputs gradation voltages in accordance with image data.
A specific example of such a decoder circuit of the tournament system is shown in FIG. 6. A decoder circuit 110 shown in FIG. 6 is a decoder circuit used in an LCD drive apparatus for 1024 gradation display.
The decoder circuit 110 includes an NMOS region 112 and a PMOS region 114. The NMOS region 112 has a hierarchical structure of five hierarchies made of a MOS transistor group, in which plural NMOS transistors are arrayed in a tournament manner. The PMOS region 114 has a hierarchical structure of five hierarchies made of a MOS transistor group, in which plural PMOS transistors are arrayed in a tournament manner.
In the NMOS region 112, ON/OFF of the NMOS transistors is controlled by predecode signals inputted to four predecode signal lines in each hierarchy (a first hierarchy: predecode signal lines DA00 to DA11, a second hierarchy: predecode signal lines DB00 to DB11, a third hierarchy: predecode signal lines DC00 to DC11, a fourth hierarchy: predecode signal lines DD00 to DD11, and a fifth hierarchy: predecode signal lines DE00 to DE11).
In the PMOS region 114, ON/OFF of the PMOS transistors is controlled by predecode signals inputted to four predecode signal lines in each hierarchy (a first hierarchy: predecode signal lines XDA00 to XDA11, a second hierarchy: predecode signal lines XDB00 to XDB11, a third hierarchy: predecode signal lines XDC00 to XDC11, a fourth hierarchy: predecode signal lines XDD00 to XDD11, and a fifth hierarchy: predecode signal lines XDE00 to XDE11).
In the decoder circuit 110, with both of the NMOS region 112 and the PMOS region 114, one MOS transistor (of one channel) is turned ON by the predecode signals of the four lines in each of the hierarchies. Due thereto, a gradation voltage selected from gradation voltages at 1024 levels of gradation voltages VR0 to VR1023 is outputted from a decoder output terminal DECOUT.
In the decoder circuit 110, the selected gradation voltage is outputted from the decoder output terminal DECOUT. At this time, however, decoder delay may be caused by a coupling capacity.
For example, when a node A 160, which is wiring between MOS transistors of the decoder circuit 110, and wiring of the decoder output DECOUT are close to each other (especially when they are adjacent and parallel to each other), a coupling capacity is caused in the node A 160. Hereinafter, a specific example of the case where the coupling capacity is caused is described. As shown in FIG. 7, when the decoder circuit 110 is laid out as shown in the figure, the node A 160 and wiring 164 of the decoder output DECOUT are close to each other. Due thereto, when the decoder output DECOUT (a gradation voltage) is outputted via other wiring and the wiring 164 without passing through the node A 160, a coupling capacity C1 is caused in the node A 160. Referring to FIG. 8, a specific example in the foregoing case is described as a case where in the decoder circuit 110 in a layout diagram of FIG. 7, a gradation voltage VR540 (a gradation signal indicating the VR540) is selected by the predecode signal to be outputted from the output terminal of the decoder output DECOUT.
FIG. 8 shows only output channels of gradation voltages VR28, VR284, VR540, and VR796 in the decoder circuit 110. When the gradation voltage VR540 is outputted from the output terminal of the decoder output DECOUT, NMOS transistors in the NMOS region 112 with the predecode signal lines DA00, DB11, DC01, DD00 connected to gates thereof are put into an ON state. Moreover, NMOS transistors 1451, 1452, 1454 with the predecode signal lines DE00, DE01, DE11 connected to gates thereof are put into an OFF state. Accordingly, an NMOS transistor 1453 with the predecode signal line DE10 connected to a gate thereof is put into an ON state.
On the other hand, PMOS transistors in the PMOS region 114 with the predecode signal lines XDA00, XDB11, XDC01, XDD00 connected to gates thereof are put into an ON state. Moreover, PMOS transistors 1551, 1552, 1554 with the predecode signal lines XDE00, XDE01, XDE11 connected to gates thereof are put into an OFF state. Accordingly, a PMOS transistor 1553 with the predecode signal line XDE10 connected to a gate thereof is put into an ON state.
Accordingly, the gradation voltage VR540 passes through NMOS transistors 141540, 142136, 14334, 14411, 1453, and the wiring 164. The gradation voltage VR540 also passes through PMOS transistors 151540, 152136, 15334, 15411, 1553, and the wiring 165. Further, the gradation voltage VR540 is outputted from the output terminal of the decoder output DECOUT.
When a voltage value of the decoder output DECOUT raises, electric charges are accumulated in the node A 160 by the caused coupling capacity C1. As a result, the voltage value of the node A 160 rises.
Normally, the raised voltage value of the note A 160 is immediately let out to a VR796 side through NMOS transistors 141796, 142200, 14350, 14416 (in FIG. 8, the NMOS transistors inside a region of a dashed line C). Accordingly, no defect occurs. However, when Vgs≈VDD-Vt (Vt: a threshold voltage) in the NMOS transistors 141796, 142200, 14350, 14416, these NMOS transistors are in a high resistance state where gates are ON. Due thereto, electric charges accumulated in the node A 160 are slowly discharged. As a result, the voltage value drops gradually (refer to a specific example shown in (1) of FIG. 9).
With the voltage drop of the node A 160, a voltage value of the decoder output DECOUT is pulled by the coupling capacity C1, so that convergence at a target voltage (selected gradation voltage) is delayed (refer to (2) and (3) of FIG. 9). In the example shown in FIG. 9, when the voltage value of the decoder output DECOUT comes close to a range of about −5 mV from the target voltage, an amount of current flowing from the VR540 becomes minute. Due thereto, the voltage value is overwhelmed by the coupling capacity C1, resulting in delay of convergence at the target voltage. As a result, the delay of the decoder output is caused.